plcc top view at28c17 16k (2k x 8) cmos e 2 prom features fast read access time - 150 ns fast byte write - 200 m s or 1 ms self-timed byte write cycle internal address and data latches internal control timer automatic clear before write direct microprocessor control data polling ready/ busy open drain output low power 30 ma active current 100 m a cmos standby current high reliability endurance: 10 4 or 10 5 cycles data retention: 10 years 5v 10% supply cmos & ttl compatible inputs and outputs jedec approved byte wide pinout commercial and industrial temperature ranges description the at28c17 is a low-power, high-performance electrically erasable and program- mable read only memory with easy to use features. the at28c17 is a 16k memory organized as 2,048 words by 8 bits. the device is manufactured with atmels reliable nonvolatile cmos technology. (continued) note: plcc package pins 1 and 17 are dont connect. pdip, soic top view pin name function a0 - a10 addresses ce chip enable oe output enable we write enable i/o0 - i/o7 data inputs/outputs rdy/ busy ready/ busy output nc no connect dc dont connect pin configurations 0541a at28c17 2-183
block diagram temperature under bias................. -55c to +125c storage temperature...................... -65c to +150c all input voltages (including nc pins) with respect to ground ................... -0.6v to +6.25v all output voltages with respect to ground .............-0.6v to v cc + 0.6v voltage on oe and a9 with respect to ground ................... -0.6v to +13.5v *notice: stresses beyond those listed under absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indi- cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings* the at28c17 is accessed like a static ram for the read or write cycles without the need of external components. during a byte write, the address and data are latched in- ternally, freeing the microprocessor address and data bus for other operations. following the initiation of a write cy- cle, the device will go to a busy state and automatically clear and write the latched data using an internal control timer. the device includes two methods for detecting the end of a write cycle, level detection of rdy/ busy and data polling of i/o 7 . once the end of a write cycle has been detected, a new access for a read or a write can begin. the cmos technology offers fast access times of 150 ns at low power dissipation. when the chip is deselected the standby current is less than 100 m a. atmels 28c17 has additional features to ensure high quality and manufacturability. the device utilizes error cor- rection internally for extended endurance and for im- proved data retention characteristics. an extra 32-bytes of e 2 prom are available for device identification or tracking. description (continued) 2-184 at28c17
device operation read: the at28c17 is accessed like a static ram. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in a high im- pedance state whenever ce or oe is high. this dual line control gives designers increased flexibility in preventing bus contention. byte write: writing data into the at28c17 is similar to writing into a static ram. a low pulse on the we or ce input with oe high and ce or we low (respectively) initi- ates a byte write. the address location is latched on the last falling edge of we (or ce); the new data is latched on the first rising edge. internally, the device performs a self- clear before write. once a byte write has been started, it will automatically time itself to completion. once a pro- gramming operation has been initiated and for the dura- tion of t wc , a read operation will effectively be a polling operation. fast byte write: the at28c17e offers a byte write time of 200 m s maximum. this feature allows the entire device to be rewritten in 0.4 seconds. ready/ busy: pin 1 is an open drain ready/ busy output that can be used to detect the end of a write cycle. rdy/ busy is actively pulled low during the write cycle and is released at the completion of the write. the open drain connection allows for or-tying of several devices to the same rdy/ busy line. data polling: the at28c17 provides data poll- ing to signal the completion of a write cycle. during a write cycle, an attempted read of the data being written results in the complement of that data for i/o 7 (the other outputs are indeterminate). when the write cycle is fin- ished, true data appears on all outputs. write protection: inadvertent writes to the device are protected against in the following ways. (a) v cc sense if v cc is below 3.8v (typical) the write function is inhibited. (b) v cc power on delay once v cc has reached 3.8v the device will automatically time out 5 ms (typical) before allowing a byte write. (c) write inhibit holding any one of oe low, ce high or we high inhibits byte write cycles. chip clear: the contents of the entire memory of the at28c17 may be set to the high state by the chip clear operation. by setting ce low and oe to 12 volts, the chip is cleared when a 10 msec low pulse is applied to we. device identification: an extra 32-bytes of e 2 prom memory are available to the user for device identification. by raising a9 to 12 0.5v and using ad- dress locations 7e0h to 7ffh the additional bytes may be written to or read from in the same manner as the regular memory array. at28c17 2-185
symbol parameter condition min max units i li input load current v in = 0v to v cc + 1v 10 m a i lo output leakage current v i/o = 0v to v cc 10 m a i sb1 v cc standby current cmos ce = v cc - 0.3v to v cc + 1.0v 100 m a i sb2 v cc standby current ttl ce = 2.0v to v cc + 1.0v com. 2 ma ind. 3 ma i cc v cc active current ac f = 5 mhz; i out = 0 ma ce = v il com. 30 ma ind. 45 ma v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage i ol = 2.1 ma = 4.0 for rdy/ busy .4 v v oh output high voltage i oh = -400 m a 2.4 v dc characteristics mode ce oe we i/o read v il v il v ih d out write (2) v il v ih v il d in standby/write inhibit v ih x (1) x high z write inhibit x x v ih write inhibit x v il x output disable x v ih x high z chip erase v il v h (3) v il high z 3. v h = 12.0v 0.5v. notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms. operating modes at28c17-15 operating temperature (case) com. 0c - 70c ind. -40c - 85c v cc power supply 5v 10% dc and ac operating range 2-186 at28c17
at28c17-15 symbol parameter min max units t acc address to output delay 150 ns t ce (1) ce to output delay 150 ns t oe (2) oe to output delay 10 70 ns t df (3, 4) ce or oe high to output float 0 50 ns t oh output hold from oe, ce or address, whichever occurred first 0ns ac read characteristics notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce whichever occurs first (c l = 5 pf). 4. this parameter is characterized and is not 100% tested. ac read waveforms (1, 2, 3, 4) t r , t f < 20 ns input test waveforms and measurement level output test load typ max units conditions c in 46pfv in = 0v c out 812pfv out = 0v pin capacitance (f = 1 mhz, t = 25c) (1) note: 1. this parameter is characterized and is not 100% tested. at28c17 2-187
symbol parameter min typ max units t as , t oes address, oe set-up time 10 ns t ah address hold time 50 ns t wp write pulse width ( we or ce) 100 1000 ns t ds data set-up time 50 ns t dh , t oeh data, oe hold time 10 ns t cs , t ch ce to we and we to ce set-up and hold time 0 ns t db time to device busy 50 ns t wc write cycle time at28c17 0.5 1.0 ms at28c17e 100 200 m s ac write characteristics ac write waveforms we controlled ce controlled 2-188 at28c17
symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns data polling characteristics (1) notes: 1. these parameters are characterized and not 100% tested. 2. see ac read characteristics. data polling waveforms chip erase waveforms t s = t h = 1 m sec (min.) t w = 10 msec (min.) v h = 12.0v 0.5v at28c17 2-189
2-190 at28c17
t acc (ns) i cc (ma) ordering code package operation range active standby 150 30 0.1 at28c17(e)-15jc 32j commercial at28c17(e)-15pc 28p6 (0 c to 70 c) at28c17(e)-15sc 28s 45 0.1 at28c17(e)-15ji 32j industrial at28c17(e)-15pi 28p6 (-40 c to 85 c) at28c17(e)-15si 28s 250 30 0.1 at28c17-w die commercial (0 c to 70 c) ordering information (1) notes: 1. see valid part number table below. 2. the 28c17 200 ns and 250 ns speed selections have been removed from valid selections table and are replaced by the faster 150 ns t aa offering. 3. the 28c17 ceramic and lcc package offerings have been removed. new designs should utilize the 28c256 ceramic offerings. the following table lists standard atmel products that can be ordered. device numbers speed package and temperature combinations at28c17 15 jc, ji, pc, pi, sc, si at28c17e 15 jc, ji, pc, pi, sc, si at28c17 - w valid part numbers package type 32j 32 lead, plastic j-leaded chip carrier (plcc) 28p6 28 lead, 0.600" wide, plastic dual inline package (pdip) 28s 28 lead, 0.300" wide, plastic gull wing, small outline (soic) w die options blank standard device: endurance = 10k write cycles; write time = 1 ms e high endurance option: endurance = 100k write cycles; write time = 200 m s at28c17 2-191
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